Principal Software Engineer (Verification Development) | Cadence Design Systems | Ahmedabad, Gujarat, India

Position: Principal Software Engineer (Verification Development)

Location: Ahmedabad, Gujarat, India

Job Description

Qualification and Skills

BE/BTech/ME/MS/MTech in Computer Science/Electronics
7+ years of experience in Verification
Expertise in one or more domains – C, UVM, System Verilog
Must possess strong written, verbal and presentation skills
Ability to establish a close working relationship with both customer peers and management
Explore what’s possible to get the job done, including creative use of unconventional solutions
Work effectively across functions and geographies
Push to raise the bar while always operating with integrity

Good working knowledge of various verification concepts such as Verification architecture, coverage, checkers, test plan etc.
Knowledge of Verification environments based on UVM, System Verilog
Should have participated in building IP/full chip verification environments, verification planning and closure process.
Domain expertise in NVMe, various DRAM PHY Memory Interfaces like DDR4/5, LPDDR4/5, HBM3, GDDR7, PCIe or any other storage protocol would be a strong plus
Programming skills: C, Verilog, System Verilog mandatory. Experience in modeling in C++, Object-oriented code approach, algorithms and data structure would be a strong plus.
Very good debugging and analytical skills
Should have good communication skills and should be a good team player

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